Clock signal may be generated by a phase locked loop (PLL). A clock signal may be distributed throughout a processor to facilitate the processor's operation. For example, state elements (e.g., Flip-flops, latches, etc.) located at different points in the processor die may function synchronously by operating in accordance with the clock signal. When a large, sudden current requirement occurs, the on-die voltage supply provided to the state elements may “droop” (e.g., for a few nanoseconds) while the PLL continues to generate a clock signal with a fixed frequency. Note that other voltage droop events may last even longer. To ensure that the processor functions during these droop events, a high voltage margin may be provided for the state elements even during normal operation (e.g., when there is no voltage droop). That is, the processor is designed to operate at both the highest specified frequency and at the lowest potential voltage simultaneously.
Since power has a quadratic dependence on voltage, a significant amount of power may be wasted during normal operation to ensure functionality during the infrequent voltage droops. Moreover, as processor speed and integration increases, the amount of power that is required may become a limiting factor. For example, the costs of designing and cooling a processor that consumes a significant amount of power may become impractical.
Existing analog PLLs implement Adaptive Frequency Scaling (AFS) to compensate for power supply voltage droops and overshoots. One such AFS technique is described by U.S. Pat. No. 6,922,111. Current analog implementation of AFS technique directly modulates the VCO supply through resistive coupling of the digital power supply. The current analog implementation does not fully exploit the full benefits of the AFS technique at lower voltages and lower frequencies.